CMOS four-quadrant multiplier using triode transistors based on regulated cascode structure

Author

Tsay, Jiann-Horng ; Liu, Shen-Iuan ; Chen, Jiann-Jong ; Wu, Yan-Pei

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

31

Issue

12

fYear

1995

fDate

6/8/1995 12:00:00 AM

Firstpage

962

Lastpage

963

Abstract

A new CMOS four-quadrant multiplier consisting of two MOS transistors operated in the triode region with regulated cascode structures is introduced. This circuit employs the essential property that MOS transistors are bi-directional (or symmetric) devices. Simulation results show that for supply voltages of ±3 V, this circuit has <1% linearity error for a differential input range up to ±1.8 V. Total harmonic distortion (THD) with a 1.8 V (peak) input signal at either input terminal with a ±1.8 V DC voltage at the other terminal is less than 1%. The simulated -3dB bandwidth of this multiplier is -17 MHz

Keywords

CMOS integrated circuits; errors; harmonic distortion; multiplying circuits; simulation; triodes; 1.8 V; 17 MHz; 3 V; CMOS four-quadrant multiplier; DC voltage; MOS transistors; bi-directional; differential input range; input terminal; linearity error; peak input signal; regulated cascode structure; regulated cascode structures; simulation results; supply voltages; symmetric devices; total harmonic distortion; triode region; triode transistors;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19950638

Filename

390999