Title :
Analysis and characterization of BiCMOS for high-speed digital logic
Author :
Greeneich, Edwin W. ; McLaughlin, Kevin L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona State Univ., Tempe, AZ, USA
fDate :
4/1/1988 12:00:00 AM
Abstract :
A combined bipolar and CMOS (BiCMOS) logic gate, capable of driving large capacitive loads at high speed, is analyzed and characterized. A simple analytical model which accurately predicts the transient response of the BiCMOS gate is described. At moderate and large loads, saturation of the bipolar transistors due to collector resistance can dominate the transient response. Device scaling issues are discussed for minimizing gate delay at various loading conditions
Keywords :
VLSI; digital integrated circuits; integrated circuit technology; semiconductor device models; BiCMOS; analytical model; characterization; device scaling; driving large capacitive loads; high-speed digital logic; loading conditions; minimizing gate delay; modelling; transient response; Analytical models; BiCMOS integrated circuits; Bipolar transistors; CMOS logic circuits; CMOS technology; Delay; Logic devices; Logic gates; MOS devices; MOSFET circuits; Transient response;
Journal_Title :
Solid-State Circuits, IEEE Journal of
