DocumentCode :
796277
Title :
Parallel CRC realization
Author :
Campobello, Giuseppe ; Patanè, Giuseppe ; Russo, Marco
Author_Institution :
Dept. of Phys., Messina Univ., Italy
Volume :
52
Issue :
10
fYear :
2003
Firstpage :
1312
Lastpage :
1319
Abstract :
This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from which our parallel implementation is derived. In comparison with previous works, the new scheme is faster and more compact and is independent of the technology used in its realization. In our solution, the number of bits processed in parallel can be different from the degree of the polynomial generator. Last, we have also developed high-level parametric codes that are capable of generating the circuits autonomously when only the polynomial is given.
Keywords :
cyclic redundancy check codes; parallel architectures; polynomials; circuits; high-level parametric codes; high-speed hardware; parallel CRC checksums; polynomial generator; recursive formula; Arithmetic; Circuit testing; Cyclic redundancy check; Data communication; Field programmable gate arrays; Hardware; Logic circuits; Polynomials; Transmitters; Very large scale integration;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2003.1234528
Filename :
1234528
Link To Document :
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