• DocumentCode
    796503
  • Title

    A vertically integrated tool for automated design of ΣΔ modulators

  • Author

    Medeiro, F. ; Pérez-Verdu, B. ; Rodríguez-Vázquez, A. ; Huertas, J.L.

  • Author_Institution
    Centro Nacional de Microelectron., Univ. de Sevilla, Spain
  • Volume
    30
  • Issue
    7
  • fYear
    1995
  • fDate
    7/1/1995 12:00:00 AM
  • Firstpage
    762
  • Lastpage
    772
  • Abstract
    We present a tool that starting from high-level specifications of switched-capacitor (SC) ΣΔ modulators calculates optimum specifications for their building blocks and then optimum sizes for the block schematics. At both design levels, optimization is performed using statistical techniques to enable global design and innovative heuristics for increased computer efficiency as compared with conventional statistical optimization. The tool uses an equation-based approach at the modulator level, a simulation-based approach at the cell level, and incorporates an advanced ΣΔ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: (1) a 16 b @ 16 kHz output rate second-order ΣΔ modulator; and (2) a 17 b @ 40 kHz output rate fourth-order ΣΔ modulator. Both use SC fully differential circuits and were designed using the proposed tool and manufactured in a 1.2 μm CMOS double-metal double-poly technology.
  • Keywords
    circuit CAD; circuit analysis computing; circuit optimisation; integrated circuit design; sigma-delta modulation; switched capacitor networks; ΣΔ modulators; 1.2 micron; 16 bit; 16 kHz; 17 bit; 40 kHz; automated design; behavioral simulator; computer efficiency; design space exploration; double-metal double-poly technology; equation-based approach; fully differential circuits; global design; high-level specifications; innovative heuristics; modulator level; simulation-based approach; statistical techniques; switched-capacitor networks; vertically integrated tool; CMOS technology; Circuit simulation; Computational modeling; Computerized monitoring; Design optimization; Equations; Manufacturing; Prototypes; Silicon; Space exploration;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.391115
  • Filename
    391115