An effective BIST scheme for ROM´s

Author

Zorian, Yervant ; Ivanov, André

Author_Institution

AT&T Bell Lab., Princeton, NJ, USA

Volume

41

Issue

5

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

646

Lastpage

653

Abstract

A built-in self-test (BIST) scheme for ROMs that has very high fault coverage and very small likelihood of error escape (aliasing) is described. For test generation, the scheme uses the exhaustive test technique. For output data evaluation the scheme uses both time and space compactors. Linear space compaction is performed using a multiple-input linear feedback shift register (MISR). For time compaction, nonlinear compaction (count-based) enhanced by the output data modification (ODM) technique is used. Space compaction is further enhanced by using a bidirectional MISR

Keywords

built-in self test; integrated circuit testing; read-only storage; BIST; ROMs; aliasing; bidirectional MISR; built-in self-test; data modification; error escape; exhaustive test; fault coverage; linear space compaction; multiple-input linear feedback shift register; nonlinear compaction; output data evaluation; test generation; time compaction; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Compaction; Linear feedback shift registers; Logic; Polynomials; Read only memory; System testing;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.142691

Filename

142691