DocumentCode
796616
Title
Low-power 50 Gbit/s InP HBT 1:4 demultiplexer IC with multiphase clock architecture
Author
Sano, K. ; Hirata, M. ; Murata, K. ; Yamahata, S. ; Ida, M. ; Kurishima, K. ; Enoki, T. ; Sugahara, H.
Author_Institution
NTT Photonics Labs., NTT Corp., Kanagawa, Japan
Volume
39
Issue
18
fYear
2003
Firstpage
1332
Lastpage
1334
Abstract
An InP HBT 1:4 demultiplexer IC with a multiphase clock architecture is described that reduces the number of circuit elements and power consumption while maintaining operating speed. The IC operated at 50 Gbit/s with 1.17 W power consumption at a supply voltage of -4.5 V. Compared to an IC with a conventional tree-type architecture using the same InP HBTs, the power consumption is less than half while the operating speed of 50 Gbit/s is maintained.
Keywords
III-V semiconductors; bipolar integrated circuits; clocks; demultiplexing equipment; heterojunction bipolar transistors; indium compounds; low-power electronics; -4.5 V; 1.17 W; 50 Gbit/s; InP; low-power InP HBT demultiplexer IC; multiphase clock architecture; power consumption;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20030857
Filename
1234627
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