Analogue VLSI morphological image processing circuit

Author

Morris, T.G. ; DeWeerth, S.P.

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

31

Issue

23

fYear

1995

fDate

11/9/1995 12:00:00 AM

Firstpage

1998

Lastpage

1999

Abstract

An analogue VLSI circuit that performs morphological image processing operations on the focal plane is presented. The circuit has been fabricated using a standard digital CMOS process. We exploit the parallelism of morphological image processing operations by using the massively parallel architecture of analogue VLSI arrays, achieving both high-speed and low-power computation. The analogue circuit presented computes the grey-scale morphological operation of dilation. This system also allows for programmability of the structuring element used in the dilation operation

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; image processing equipment; image segmentation; mathematical morphology; object detection; parallel architectures; CMOS process; analogue VLSI circuit; dilation; focal plane; grey-scale image processing; grey-scale morphological operation; high-speed computation; low-power computation; massively parallel architecture; morphological image processing circuit; nonlinear image processing; programmability;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19951367

Filename

490598