DocumentCode :
796769
Title :
Fast Decimal Floating-Point Division
Author :
Nikmehr, Hooman ; Phillips, Braden ; Lim, Cheng-Chew
Author_Institution :
Dept. of Comput. Eng., Bu Ali Sina Univ., Hamedan
Volume :
14
Issue :
9
fYear :
2006
Firstpage :
951
Lastpage :
961
Abstract :
A new implementation for decimal floating-point (DFP) division is introduced. The algorithm is based on high-radix SRT division The SRT division algorithm is named after D. Sweeney, J. E. Robertson, and T. D. Tocher. with the recurrence in a new decimal signed-digit format. Quotient digits are selected using comparison multiples, where the magnitude of the quotient digit is calculated by comparing the truncated partial remainder with limited precision multiples of the divisor. The sign is determined concurrently by investigating the polarity of the truncated partial remainder. A timing evaluation using a logic synthesis shows a significant decrease in the division execution time in contrast with one of the fastest DFP dividers reported in the open literature
Keywords :
floating point arithmetic; DFP division; decimal signed-digit format; fast decimal floating-point division; high-radix SRT division; logic synthesis; quotient digit; truncated partial remainder; Application software; Banking; Computer errors; Databases; Digital arithmetic; Hardware; Humans; Insurance; Logic; Timing; Binary-coded decimal (BCD); decimal floating-point (DFP) arithmetic; digit recurrence division;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2006.884047
Filename :
1715328
Link To Document :
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