Title :
An Asynchronous Low-Power High-Performance Sequential Decoder Implemented With QDI Templates
Author :
Ozdag, Recep O. ; Beerel, Peter A.
Author_Institution :
Electr. Eng. Dept., Univ. of South California, Los Angeles, CA
Abstract :
This paper presents the design of a channel-based asynchronous sequential decoder implemented with quasi-delay-insensitive templates. The Powermill simulation results in TSMC 0.25-CMOS technology show that the circuit runs at 430 MHz and consumes 32 mW. Techniques to effectively partition and implement the top level design, the implementation of fast shift registers, memories, and various other structures are discussed. Compared to a previously designed synchronous Fano decoder, the asynchronous version consumes 1/3 the power and runs at 2.15 times the speed assuming standard process normalization. The design also highlights the introduction of a standard-cell library and back-end design flow for asynchronous designs based on precharged half buffer (PCHB) templates
Keywords :
CMOS logic circuits; UHF integrated circuits; asynchronous circuits; decoding; low-power electronics; 0.25 micron; 32 mW; 430 MHz; CMOS; QDI templates; TSMC; asynchronous designs; asynchronous low-power high-performance sequential decoder; back-end design flow; channel-based asynchronous sequential decoder; precharged half buffer templates; quasi-delayinsensitive templates; shift registers; standard-cell library; top level design; Algorithm design and analysis; Application specific integrated circuits; Asynchronous communication; Circuit simulation; Convolution; Decoding; Libraries; Pipeline processing; Shift registers; Viterbi algorithm; Asynchronous; QDI; asynchronous library design; convolutional encoder; fano algorithm; precharged half buffer (PCHB);
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2006.884049
