Technique for Obtaining Radiation Hardened Semiconductor Devices by Irradiating Wafers

Many military electronic systems are required to function during or after exposure to a nuclear radiation environment. Bipolar transistors and related integrated circuits are very sensitive to the effects of neutron damage that decrease transistor current gain and increase transistor saturation resistance. These effects may result in post-irradiation circuit failure at neutron fluences below radiation specification, particularly when ordinary neutron effect screening techniques are used. This paper describes a screening technique that assures postirradiation electrical performance of semiconductor piece parts, eliminates the problem associated with the so-called "maverick" or unpredictable transistor, and monitors the effects of manufacturing process changes. This technique is economically attractive when applied on a lot-to-lot basis. Nuclear radiation is an additional environment to be considered in production lot-to-lot semiconductor quality assurance. For any environment, acceptable products are determined by 100 percent screening tests to the specification level (Group A) followed by sample environmental tests (Group B) that measure the level of success of the initial screening procedure. If silicon wafers have been subjected to reactor radiation, Group A and Group B screening techniques can be used to screen semiconductor devices for radiation effects on electrical parameters. This is accomplished by irradiating and thermal annealing the in-process silicon wafers, subjecting them to Group A tests and then subjecting samples to Group B tests. The screening technique has been demonstrated practical and repeatable through use of the White Sands Missile Range Fast Burst Reactor (FBR) and the University of Arizona TRIGA Reactor.