Transient behavior of load transformer during subcycle bus transfer

Fast (subcycle) bus transfer by means of a static transfer switch (STS) requires short time intervals for the detection and transfer process. Due to these time intervals, the load transformer is subjected to a transient process which can be accompanied by large transient current components through the transformer. The transient current, in turn, can cause voltage sag at the load terminal. The STS control logic must be able to distinguish such a voltage sag from those due to the supply disturbances and not disconnected from the load. This paper provides simplified analytical expressions to predict F of the load transformer which can be used to estimate the corresponding voltage sag. The PSCAD/EMTDC-based digital simulation of the actual nonlinear system is also carried out to substantiate the validity of the analytical expressions.