A highly robust process integration with scaled ONO interpoly dielectrics for embedded nonvolatile memory applications

Author

Shum, Danny P. ; Tseng, Hsing-Huang ; Paulson, Wayne M. ; Chang, Ko-Min ; Tobin, Philip J.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

Volume

Issue

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

1376

Lastpage

1377

Abstract

We have developed a process sequence for a flash EEPROM memory embedded in an advanced microcontroller circuit. This process simultaneously forms a thick top oxide on the interpoly ONO dielectric in the memory array and a stacked gate-oxide for the logic transistors. We have fabricated one-transistor, flash bit-cells with good data retention characteristics that incorporate a 17 nm ONO film along with high-quality stacked gate oxides

Keywords

CMOS memory circuits; EPROM; cellular arrays; dielectric thin films; microcontrollers; 17 nm; data retention characteristics; embedded nonvolatile memory applications; flash EEPROM memory; flash bit-cells; memory array; microcontroller circuit; process integration; scaled ONO interpoly dielectrics; stacked gate-oxide; thick top oxide; Circuits; Cleaning; Dielectrics; EPROM; Logic arrays; Logic gates; Microcontrollers; Nonvolatile memory; Resists; Robustness;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.391224

Filename

391224

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=797443