DocumentCode :
79811
Title :
Arithmetic-Based Binary-to-RNS Converter Modulo 
for 
-bit Dynamic Range
Author :
Miguens Matutino, Pedro ; Chaves, Ricardo ; Sousa, Leonel
Author_Institution :
High Inst. of Eng. of Lisbon, Univ. de Lisboa, Lisbon, Portugal
Volume :
23
Issue :
3
fYear :
2015
fDate :
Mar-15
Firstpage :
603
Lastpage :
607
Abstract :
In this brief, a read-only-memoryless structure for binaryto-residue number system (RNS) conversion modulo (2n ±k} is proposed. This structure is based only on adders and constant multipliers. This brief is motivated by the existing (2n ± k} binary-to-RNS converters, which are particular inefficient for larger values of n. The experimental results obtained for 4n and 8n bits of dynamic range suggest that the proposed conversion structures are able to significantly improve the forward conversion efficiency, with an AT metric improvement above 100%, regarding the related state of the art. Delay improvements of 2.17 times with only 5% area increase can be achieved if a proper selection of the (2n ± k} moduli is performed.
Keywords :
adders; residue number systems; adders; arithmetic-based binary-to-RNS converter modulo; conversion efficiency; jn-bit dynamic range; multipliers; read-only-memoryless structure; residue number system; Adders; Delays; Design automation; Periodic structures; Read only memory; Very large scale integration; Arithmetic; binary-to-RNS; forward conversion; residue number systems; residue number systems.;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2014.2314174
Filename :
6798674
Link To Document :
