DocumentCode :
798181
Title :
A VLSI architecture for the alternative subsampling-based block matching algorithm
Author :
Jung, Hae-Kwan ; Hong, Chun-Pyo ; Choi, Jin-Soo ; Ha, Yeong-Ho
Author_Institution :
Dept. of Electron. Eng., Kyungpook Nat. Univ., Taegu, South Korea
Volume :
41
Issue :
2
fYear :
1995
fDate :
5/1/1995 12:00:00 AM
Firstpage :
239
Lastpage :
247
Abstract :
A VLSI architecture of the block matching algorithm based on the alternative subsampling method for motion estimation is proposed. The alternative subsampling method reduces the computational complexity by alternatively subsampling the number of pixels within the blocks used to estimate motion vectors, whereas conventional methods limit the number of locations searched. Simulation results show that the performance of this method is very close to full search algorithm. For a subsampling factor of N, this approach can achieve approximately N/2 times of calculation with an additional small overhead associated with the address generator and temporary buffer. In addition, this architecture has about a half of the silicon area compared to Yang´s (1989) architecture
Keywords :
VLSI; buffer circuits; computational complexity; digital signal processing chips; image matching; image sampling; image sequences; motion estimation; video coding; VLSI architecture; address generator; computational complexity reduction; full search algorithm; motion estimation; motion vectors; overhead; performance; simulation results; subsampling factor; subsampling-based block matching algorithm; temporary buffer; video sequences coding; Computational complexity; Computational modeling; Computer architecture; Computer science; Computer simulation; HDTV; Motion estimation; Sampling methods; Very large scale integration; Video sequences;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/30.391351
Filename :
391351
Link To Document :
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