A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations

Author

Karathanasis, Haralambos C.

Author_Institution

Intracom S.A., Peania Attika, Greece

Volume

41

Issue

2

fYear

1995

fDate

5/1/1995 12:00:00 AM

Firstpage

263

Lastpage

272

Abstract

In this paper, we first propose an algorithm for computing the DCT and IDCT using rotations. Then, based on the proposed algorithm, we present a unified VLSI architecture for the real-time implementation of the forward and inverse 8×8 DCT and DST. The rotation circuit which is the main processing unit of this architecture, is realized with distributed arithmetic using the binary offset coding strategy. Exploitation of the rotation properties results in a reduction of the total ROM requirements of the unified architecture, to less than 10% of those of the typical distributed arithmetic DCT/IDCT implementations, thus yielding considerable area savings. Moreover, the proposed architecture can achieve the processing power of 100 Mpixels/sec, if implemented in 0.8 μ CMOS technology, which is sufficient for the real-time processing of HDTV signals

Keywords

CMOS digital integrated circuits; VLSI; digital arithmetic; digital signal processing chips; discrete cosine transforms; high definition television; read-only storage; real-time systems; transforms; video signal processing; 0.8 micron; CMOS technology; DCT; HDTV signals; IDCT; algorithm; area savings; binary offset coding strategy; forward/inverse DCT; forward/inverse DST; low ROM distributed arithmetic implementation; processing power; real-time implementation; rotation circuit; unified VLSI architecture; Arithmetic; CMOS process; CMOS technology; Circuits; Computer architecture; Discrete cosine transforms; HDTV; Read only memory; Signal processing; Very large scale integration;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.391354

Filename

391354