Requirements for accurate MOS-SOI device simulations

Author

Rios, Rafael ; Amantea, Robert ; Smeltzer, Ronald K. ; Rothwarf, Allen

Author_Institution

David Sarnoff Res. Center, Princeton, NJ, USA

Volume

39

Issue

3

fYear

1992

fDate

3/1/1992 12:00:00 AM

Firstpage

581

Lastpage

586

Abstract

Simulations of the electrical behavior of MOS-SOI devices pose a difficult numerical problem due to the floating substrate region. The numerical analysis techniques required to solve the floating region problem are discussed. Models for the carrier mobilities and lifetime variation with depth into the silicon film are introduced to fit measured SOS device data. The current-voltage characteristics of SOS transistors, including the kink, are accurately simulated and compared to measurements. The floating potential variation with applied gate and drain bias predicted by the simulation is discussed

Keywords

insulated gate field effect transistors; semiconductor device models; semiconductor-insulator boundaries; MOS-SOI devices; MOSFET; SOS device data; SOS transistors; carrier mobilities; current-voltage characteristics; device simulations; drain bias; electrical behavior; floating potential variation; floating region problem; floating substrate region; gate bias; kink; lifetime variation; modelling; numerical analysis; numerical problem; CMOS logic circuits; CMOS technology; Integrated circuit technology; Isolation technology; Numerical analysis; Poisson equations; Semiconductor films; Silicon; Smelting; Substrates;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.123481

Filename

123481