Analytical approach to evaluate thermal reduction effects of peripheral structures on microwave power GaAs device chips

Thermal analysis of microwave power GaAs device chips has been presented that features analytical simplicity yet gives quantitative evaluation of thermal reduction effects of two kinds of chip peripheral structures, via-holes and bumps. To calculate T_max (maximum temperature) and R_th (thermal resistance), the Laplace equation has been solved for a basic chip model under boundary conditions appropriate to peripheral structures. The chip model consisted of three layers features having heat sources at interface of layer 2 and 3. An approximate method for the analysis of field effect transistor (FET) unit with bumps has been newly proposed. A good agreement has been found between the calculated and measured R_th and its reduction effect, verifying the usefulness of the present analysis in the thermal design of device chips.