Title :
A steady-state VDMOS transistor model
Author :
Paredes, Jacinto ; Hidalgo, Salvador ; Berta, Francisco ; Fernandez, Juan ; Rebollo, Jose ; Millan, Jose
Author_Institution :
Centro Nacional de Microelectron., Barcelona, Spain
fDate :
3/1/1992 12:00:00 AM
Abstract :
An analytical model is proposed in order to explain the DC VDMOS transistor performance. It accounts for the device linear region, and the quasi-saturation effect is included in the formulation by considering the carrier velocity saturation at high electric field values. Electric field and majority-carrier distributions can be deduced from the model which agree with the results obtained from two-dimensional simulations. This formulation predicts a majority-carrier excess inside the epilayer even before the carrier velocity saturation is achieved. Interdigitated VDMOS transistors have been fabricated and two-dimensional simulations have been carried out in order to check the output characteristics against the proposed model
Keywords :
carrier density; high field effects; insulated gate field effect transistors; semiconductor device models; DC performance; VDMOS transistor model; analytical model; carrier velocity saturation; device linear region; electric field distribution; epilayer; high electric field values; interdigitated transistors; majority-carrier distributions; output characteristics; quasi-saturation effect; steady-state model; two-dimensional simulations; Analytical models; Doping; Electrodes; Epitaxial layers; MOSFETs; Physics; Region 7; Semiconductor process modeling; Steady-state; Surface resistance;
Journal_Title :
Electron Devices, IEEE Transactions on
