Title :
Designing multioperand modular adders
Author :
Alia, G. ; Martinelli, E.
Author_Institution :
Dipartimento di Ingegneria dell´´Inf., Pisa Univ., Italy
fDate :
1/4/1996 12:00:00 AM
Abstract :
The problem of designing efficient multioperand modular adders is approached. A carry-save adder tree is used allowing a response time lower than values in the literature, without restrictions regarding modules. Moreover it is shown that a structure such as the proposed one is suitable for evaluating |X|m within a logarithmic time
Keywords :
adders; logic design; residue number systems; carry-save adder tree; design; logarithmic time; multioperand modular adders; response time;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960026
