On the realizability and synthesis of delay-insensitive behaviors

Author

Leung, S.C. ; Li, H.F.

Author_Institution

Dept. of Electron. Eng., City Polytech. of Hong Kong, Kowloon, Hong Kong

Volume

14

Issue

7

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

833

Lastpage

848

Abstract

This paper presents six properties, each of which, if satisfied by all the basic circuit elements used in synthesis, will also be satisfied by any delay-insensitive (DI) behavior realized by those circuit elements. Six relevant theorems are proved. The DI behaviors of classical circuit elements (e.g., AND, OR, inverter, merge, etc.) are then examined. It is found that they all satisfy the so called unique successor set (USS) property. As a result, it is proved that any DI behavior realized by a network of classical circuit elements necessarily exhibits the USS property. Some new circuit elements are needed to realize arbitrary DI behaviors (e.g., those that do not exhibit the USS property). A set of circuit elements is proposed. It is shown that these circuit elements are sufficient to implement any determinate finite state DI system

Keywords

VLSI; asynchronous circuits; delays; finite state machines; timing; VLSI; arbitrary DI behaviors; asynchronous circuits; circuit elements; delay-insensitive behaviors; determinate finite state DI system; self-timed circuit; timing problems; unique successor set; Circuit synthesis; Clocks; Delay systems; Inverters; Joining processes; Latches; Robustness; Timing; Very large scale integration; Wires;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.391731

Filename

391731