A preprocessor for improving channel routing hierarchical pin permutation

Author

Chen, C. Y Roger ; Hou, Cliff Yungchin ; Carlson, Bradley S.

Author_Institution

Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA

Volume

14

Issue

7

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

896

Lastpage

903

Abstract

In standard cell design, many cell terminals and gates are permutable, and it is important for a channel router to take advantage of this to obtain better results. An efficient hierarchical algorithm is presented to determine the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. Experimental results show that our proposed algorithm considerably reduces the number of tracks and vias, and its time complexity is linear in the number of cell terminals

Keywords

VLSI; circuit layout CAD; computational complexity; integrated circuit layout; logic CAD; network routing; channel routeing; channel router; hierarchical algorithm; hierarchical pin permutation; permutable cell terminals; permutable gates; preprocessor; standard cell design; time complexity; Libraries; Programmable logic arrays; Programmable logic devices; Rivers; Routing; Simulated annealing; Very large scale integration;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.391738

Filename

391738