Title :
A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control
Author :
Jang, Young-Chan ; Bae, Jun-Hyun ; Park, Hong-June
Author_Institution :
Dept. of Electr. & Comput. Eng, Pohang Inst. of Sci. & Technol.
Abstract :
A digital pulsewidth control loop (PWCL) with a fixed-delay rising edge and digital stability control is proposed for multiphase clock applications. In the duty-cycle tracking mode, the linear range of the input duty cycle was measured to be 28%-70%, with a maximum linearity deviation of 0.5%. In the duty-cycle correction mode, the correction range of the input duty cycle was measured to be 25%-75%, with the output duty cycle within 50 plusmn 0.4%. The chip was fabricated by using a 0.25-mum CMOS process with a 2.5-V supply. The chip area and the power consumption were 200 mumtimes250 mum and 18 mW at an input clock frequency of 1.0 GHz, respectively
Keywords :
CMOS digital integrated circuits; circuit stability; delays; 0.25 micron; 1.0 GHz; 18 mW; 2.5 V; CMOS process; digital PWCL; digital pulsewidth control loop; digital stability control; duty cycle correction mode; duty cycle tracking mode; fixed delay rising edge; input duty cycle; maximum linearity deviation; multiphase clock applications; Circuit stability; Clocks; Delay effects; Digital control; Driver circuits; Linearity; Phase locked loops; Pulse width modulation; Semiconductor device measurement; Space vector pulse width modulation; Digital PWCL; fixed-delay rising edge; pulsewidth control loop (PWCL); stability;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2006.882186