• DocumentCode
    799587
  • Title

    Effect of nanotopography in direct wafer bonding: modeling and measurements

  • Author

    Turner, K.T. ; Spearing, S.M. ; Baylies, W.A. ; Robinson, M. ; Smythe, R.

  • Author_Institution
    Massachusetts Inst. of Technol., Cambridge, MA, USA
  • Volume
    18
  • Issue
    2
  • fYear
    2005
  • fDate
    5/1/2005 12:00:00 AM
  • Firstpage
    289
  • Lastpage
    296
  • Abstract
    Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.
  • Keywords
    lead bonding; nanotechnology; semiconductor process modelling; surface topography measurement; 150 mm; analysis techniques; direct wafer bonding; elastic strain energy; mechanics-based models; microelectromechanical systems; nanotopography measurements; polishing processes; silicon wafers; silicon-on-insulator; surface height variations; wafer geometry feature; Adhesives; Capacitive sensors; Geometry; Manufacturing processes; Nanotopography; Semiconductor device modeling; Silicon; Surface waves; Wafer bonding; Wavelength measurement; Direct bonding; microelectromechanical systems (MEMS); nanotopography; silicon-on-insulator (SOI); wafer bonding;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2005.845009
  • Filename
    1427797