Multilevel Routing With Redundant Via Insertion

This brief presents an improved multilevel full-chip routing system which integrates the redundant via placement in the routing flow for yield and reliability enhancement. The system features a pre-coarsening stage which is equipped with fast congestion-driven L-pattern global router followed by detailed router. The L-pattern global routing benefits to the reduction of vias and thus relieves the burden of redundant via addition. In addition, a rvia-driven maze routing algorithm is also integrated in the system to improve the insertion of redundant vias. Finally a redundant via placement heuristic is adopted to enhance the completion rate. We have tested the system on a set of commonly used benchmark circuits and compared the results with a previous multilevel routing system. Besides much enhancement obtained in the aspect of redundant via placement, the system also obtains high routing completion rate, minimized total wire length and total number of vias in satisfactory runtime