Title :
Challenges in the design high-speed clock and data recovery circuits
Author_Institution :
California Univ., Los Angeles, CA, USA
fDate :
8/1/2002 12:00:00 AM
Abstract :
This article describes the challenges in the design of monolithic clock and data recovery circuits used in high-speed transceivers. Following an overview of general issues, the task of phase detection for random data is addressed. Next, Hogge (1985), Alexander (1975), and half-rate phase detectors are introduced and their trade-offs outlined. Finally, a number of clock and data recovery architectures are presented.
Keywords :
MMIC; VLSI; clocks; high-speed integrated circuits; integrated circuit design; phase detectors; synchronisation; Alexander phase detector; Hogge phase detector; VCO; VLSI; half-rate phase detectors; high-speed clock circuits design; high-speed data recovery circuits design; high-speed transceivers; jitter; lock acquisition; monolithic circuits; random data; skews; very large scale integrated technologies; Circuit noise; Clocks; Detectors; Frequency; Jitter; Phase detection; Sampling methods; Transceivers; Very large scale integration; Voltage-controlled oscillators;
Journal_Title :
Communications Magazine, IEEE
DOI :
10.1109/MCOM.2002.1024421
