Title :
Optimal fault detection for analogue circuits under manufacturing tolerances
Author :
Gielen, G. ; Wang, Z. ; Sansen, W.
Author_Institution :
Dept. Elektrotech., Katholieke Univ., Leuven, Heverlee, Belgium
fDate :
1/4/1996 12:00:00 AM
Abstract :
An optimal method for analogue fault detection is presented. Instead of using arbitrary decision windows, the method fully considers the VLSI manufacturing tolerances and mismatches to minimise the probability of erroneous test decision. A-priori simulated probability information is combined with the actual measurement data to decide whether the circuit is fault-free or faulty. Experimental results show the effectiveness of the proposed technique
Keywords :
VLSI; analogue integrated circuits; digital simulation; fault location; integrated circuit testing; production testing; VLSI; a-priori simulated probability information; analogue circuits; fault detection; manufacturing tolerances;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19960056