Author_Institution :
Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ
Abstract :
A predictive MOSFET model is critical for early circuit design research. To accurately predict the characteristics of nanoscale CMOS, emerging physical effects, such as process variations and correlations among model parameters, must be included. In this paper, a new generation of predictive technology model (PTM) is developed to accomplish this goal. Based on physical models and early-stage silicon data, the PTM of bulk CMOS is successfully generated for 130- to 32-nm technology nodes, with an Leff of as low as 13 nm. The accuracy of PTM predictions is comprehensively verified: The error of I on is below 10% for both n-channel MOS and p-channel MOS. By tuning only ten primary parameters, the PTM can be easily customized to cover a wide range of process uncertainties. Furthermore, the new PTM correctly captures process sensitivities in the nanometer regime, particularly the interactions among Leff, Vth, mobility, and saturation velocity. A website has been established for the release of PTM: http://www.eas.asu.edu/~ptm
Keywords :
CMOS integrated circuits; MOSFET; carrier mobility; integrated circuit design; nanoelectronics; semiconductor device models; 32 to 130 nm; MOSFET model; early design exploration; mobility degradation; nanoscale CMOS characteristic; physical effects; physical models; predictive technology model; process sensitivity; process uncertainty; process variation; Accuracy; CMOS process; CMOS technology; Circuit synthesis; Degradation; MOSFET circuits; Predictive models; Semiconductor device modeling; Silicon; Threshold voltage; Mobility degradation; predictive modeling; process variation; saturation velocity; threshold voltage;
