A 6 K GaAs gate array with fully functional LSI personalization

Author

Peczalski, A. ; Lee, Gene ; Betten, W.R. ; Somal, H. ; Plagens, Mark ; Biard, James R. ; Burrows, Ian ; Gilbert, Barry K. ; Thompson, Rick L. ; Naused, Barbara A. ; Karwoski, Susan M. ; Samson, Mark L. ; Zahn, Sharon K.

Author_Institution

Honeywell Syst. & Res. Center, Minneapolis, MN, USA

Volume

23

Issue

2

fYear

1988

fDate

4/1/1988 12:00:00 AM

Firstpage

581

Lastpage

590

Abstract

A 12×12 multiplier consisting of 19000 devices was successfully implemented on a 6000-gate array. A high-yield-oriented circuit design and the gate-array architecture are presented. It is shown that when temperature compensation is applied the GaAs circuit operating range can be extended over 160°C range. The backgating and dynamic (switching) noise are also discussed as the key noise-margin limiting factors. A specialized on-chip circuitry which enables on-chip measurement and fault localization in complex GaAs ICs is proposed and implemented. The high yield of the multiplier (10%) seems to be limited only by particle contamination, which indicates that the noise margin is satisfactory for the GaAs nonselfaligned depletion-mode fabrication process

Keywords

III-V semiconductors; cellular arrays; digital arithmetic; field effect integrated circuits; gallium arsenide; integrated circuit technology; integrated logic circuits; large scale integration; multiplying circuits; 160 C; GaAs; backgating; depletion-mode fabrication process; fault localization; fully functional LSI personalization; gate array; gate-array architecture; high-yield-oriented circuit design; multiplier; noise-margin limiting factors; on-chip measurement; particle contamination; semiconductors; specialized on-chip circuitry; temperature compensation; Circuit faults; Circuit noise; Circuit synthesis; Circuit testing; Contamination; Delay; Fabrication; Gallium arsenide; Integrated circuit testing; Large scale integration; Logic arrays; Out of order; Pollution measurement; Temperature distribution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.1025

Filename

1025