Title :
A continuous-time ΣΔ Modulator with reduced sensitivity to clock jitter through SCR feedback
Author :
Ortmanns, Maurits ; Gerfers, Friedel ; Manoli, Yiannos
Author_Institution :
sci-worx GmbH, Hannover, Germany
fDate :
5/1/2005 12:00:00 AM
Abstract :
This paper presents a means to overcome the high sensitivity of continuous-time sigma-delta (ΣΔ) modulators to clock jitter by using a modified switched-capacitor structure with resistive element in the continuous-time feedback digital-analog converter (DAC). The reduced sensitivity to jitter is both simulated and proven by measured results from two implemented third-order modulators. Additionally, the nonideal behavior is analyzed analytically and by simulations.
Keywords :
circuit feedback; circuit simulation; clocks; digital-analogue conversion; jitter; sensitivity; sigma-delta modulation; switched capacitor networks; clock jitter; continuous-time feedback digital-analog converter; sensitivity; sigma-delta modulator; switched-capacitor resistor feedback; switched-capacitor structure; third-order modulators; Clocks; Digital modulation; Feedback; Jitter; Pulse modulation; Pulse shaping methods; Resistors; Signal sampling; Space vector pulse width modulation; Thyristors; Clock jitter; continuous time (CT); sigma–delta (; switched-capacitor resistor (SCR) feedback;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2005.846227
