Neural network implementation using a single MOST per synapse

Author

Johnson, D.E. ; Marsland, J.S. ; Eccleston, W.

Author_Institution

Dept. of Electr. Eng. & Electron., Liverpool Univ., UK

Volume

6

Issue

4

fYear

1995

fDate

7/1/1995 12:00:00 AM

Firstpage

1008

Lastpage

1011

Abstract

A VLSI implementation of an artificial neural network using a single n-channel MOS (metal-oxide semiconductor) transistor per synapse is investigated. The simplicity of the design is achieved by using pulse width modulation to represent neural activity and by using a novel technique to manipulate negative weights. A simple multilayer perceptron (MLP) network was simulated using the SPICE circuit simulator and the performance of a hardware realization of the same MLP network was measured. Simulations and measurements are shown to agree well

Keywords

MOS analogue integrated circuits; SPICE; VLSI; circuit analysis computing; multilayer perceptrons; neural chips; pulse width modulation; SPICE circuit simulator; VLSI; multilayer perceptron; n-channel MOS transistor; negative weights; neural activity; neural network; pulse width modulation; Artificial neural networks; Circuit simulation; MOS devices; MOSFETs; Multilayer perceptrons; Neural networks; Pulse width modulation; SPICE; Space vector pulse width modulation; Very large scale integration;

fLanguage

English

Journal_Title

Neural Networks, IEEE Transactions on

Publisher

ieee

ISSN

1045-9227

Type

jour

DOI

10.1109/72.392265

Filename

392265