A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

Author

Kim, Byung-Guk ; Kim, Lee-Sup ; Park, Kwang-Il ; Jun, Young-Hyun ; Cho, Soo-In

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon

Volume

44

Issue

5

fYear

2009

fDate

5/1/2009 12:00:00 AM

Firstpage

1522

Lastpage

1530

Abstract

A DLL featuring jitter reduction techniques for a noisy environment is described. It controls a loop response mode by monitoring the magnitude of input jitter caused by supply noise. This technique varies the probability of phase error tracking. It reduces the output jitter of the DLL due to a low effective variance of input phase error and a narrow effective loop bandwidth. The DLL is implemented in a 0.13 mum CMOS process. Under noisy environments, the output clock of 1 GHz has 4.58 ps RMS and 29 ps peak-to-peak jitter.

Keywords

CMOS integrated circuits; DRAM chips; clocks; delay lock loops; jitter; CMOS process; DRAM interfaces; delay-locked loop; frequency 1 GHz; jitter reduction techniques; loop response mode; narrow effective loop; output clock; peak-to-peak jitter; phase error tracking; quadrature phase generation; size 0.13 micron; Bandwidth; Clocks; Delay lines; Frequency synchronization; Jitter; Monitoring; Noise reduction; Phase noise; Random access memory; Working environment noise; CMOS; DRAM interface; delay-locked loop (DLL); jitter;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2016993

Filename

4907314