Title :
A 65 nm CMOS 30 dBm Class-E RF Power Amplifier With 60% PAE and 40% PAE at 16 dB Back-Off
Author :
Apostolidou, Melina ; Van der Heijden, Mark P. ; Leenaerts, Domine M W ; Sonsky, Jan ; Heringa, Anco ; Volokhine, Iouri
Author_Institution :
NXP Semicond. Res., Eindhoven
fDate :
5/1/2009 12:00:00 AM
Abstract :
A 30 dBm single-ended class-E RF power amplifier (PA) is fabricated in a baseline 65 nm CMOS technology. The PA is constructed as a cascode stage formed by a standard thin-oxide device and a dedicated novel high voltage extended-drain thick-oxide device. Both devices are implemented without using additional masks or processing steps. The proposed PA uses an innovative self-biasing technique to ensure high power-added efficiency (PAE) at both high output power (Pout) and power back-off levels. At 2 GHz, the PA achieves a PAE of 60% at a Pout of 30 dBm and a PAE of 40% at 16 dB back-off. Stress tests indicate the reliability of both the novel high voltage device and the design.
Keywords :
CMOS integrated circuits; UHF integrated circuits; UHF power amplifiers; integrated circuit reliability; power integrated circuits; CMOS technology; class-E RF power amplifier; efficiency 40 percent; efficiency 60 percent; frequency 2 GHz; high voltage device reliability; high voltage extended-drain thick-oxide device; self-biasing technique; size 65 nm; stress test; thin-oxide device; CMOS technology; Impedance; Power amplifiers; Power combiners; Power generation; Radio frequency; Radiofrequency amplifiers; Substrates; Transformers; Voltage; CMOS power amplifier (PA); Cascode; HV device; class-E; driver stage; power-added efficiency (PAE); self-biasing technique;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2020680
