DocumentCode :
801924
Title :
Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 
m CMOS
Author :
Feng, Yiping ; Takemura, Gaku ; Kawaguchi, Shunji ; Kinget, Peter
Author_Institution :
Columbia Univ., New York, NY
Volume :
44
Issue :
5
fYear :
2009
fDate :
5/1/2009 12:00:00 AM
Firstpage :
1380
Lastpage :
1390
Abstract :
A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 mum CMOS process and occupies an active chip area of 1.1 mm 2. It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of -12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.
Keywords :
CMOS analogue integrated circuits; UHF amplifiers; UHF integrated circuits; UHF mixers; low noise amplifiers; CMOS front-end; LNA; current-driven passive mixer; direct-conversion front-end; double balanced mixer; frequency 2 GHz; frequency 2.1 GHz; gain 30 dB; noise figure 3.1 dB; on-chip transformer load; power 12 mW; single-ended RF input; single-ended low-noise amplifier; size 0.13 mum; voltage 1.5 V; Active noise reduction; CMOS process; Image converters; Linearity; Low-noise amplifiers; Noise figure; Performance gain; Power supplies; Prototypes; Radio frequency; Balun; WCDMA; low-noise amplifier (LNA); mixer; noise figure (NF); second-order input intercept point (IIP2);
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.2009.2015824
Filename :
4907342
Link To Document :
