A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI_pp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps_rms. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm² only. It dissipates 12.4 mW from 1 V supply.