1.1 V high speed, low power BiCMOS logic circuit

Author

Seng, Yeo Kiat ; Rofail, S.S.

Author_Institution

Sch. of Electr. & Electron. Eng., Nanyang Technol. Inst., Singapore

Volume

Issue

fYear

1995

fDate

6/22/1995 12:00:00 AM

Firstpage

1039

Lastpage

1041

Abstract

A 1.1 V full switching high speed, low power BiCMOS logic circuit is presented. It consists of nine devices and uses a noncomplementary BiCMOS process. Bootstrapping and partial charge removal techniques are employed. HSPICE simulations have shown that the new circuit outperforms both CMOS and a recently reported circuit in terms of speed and power-delay product. An analytical expression relating the pull-up delay with its device parameters is also derived

Keywords

BiCMOS logic circuits; bootstrap circuits; delays; 1.1 V; HSPICE simulations; bootstrapping; device parameters; high speed logic circuit; low power BiCMOS circuit; noncomplementary BiCMOS process; partial charge removal techniques; power-delay product; pull-up delay;

fLanguage

English

Journal_Title

Electronics Letters

Publisher

iet

ISSN

0013-5194

Type

jour

DOI

10.1049/el:19950714

Filename

392694

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=802716