DocumentCode
802811
Title
Efficient VLSI architecture for lossless data compression
Author
Kim, Y.-J. ; Kim, K.-S. ; Choi, K.-Y.
Author_Institution
Dept. of Electron. Eng., Seoul Nat. Univ., South Korea
Volume
31
Issue
13
fYear
1995
fDate
6/22/1995 12:00:00 AM
Firstpage
1053
Lastpage
1054
Abstract
An architecture for LZ1-type lossless data compression is described. The architecture is area efficient and fast. Since it exploits the locality of substring match lengths. The property has been shown experimentally for various data and buffer lengths. And an architecture based on it has been designed
Keywords
VLSI; data compression; LZ1-type lossless data compression; VLSI architecture; area efficient; buffer lengths; data lengths; fast; lossless data compression; substring match lengths;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19950703
Filename
392702
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