Characterization and design methodology for low-distortion MOSFET-C analog structures in multithreshold deep-submicrometer SOI CMOS technologies

Author

Vancaillie, Laurent ; Kilchytska, Valeria ; Alvarado, Joaquin ; Cerdeira, Antonio ; Flandre, Denis

Author_Institution

Lab. de Microelectronique, Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium

Volume

53

Issue

2

fYear

2006

Firstpage

263

Lastpage

269

Abstract

The harmonic distortion (HD) of MOSFETs operating in the triode regime is thoroughly investigated for the different device types of a multi-V_th deep-submicrometer 0.12-μm silicon-on-insulator (SOI) CMOS process. The measurements performed in a wide temperature range (25°C-220°C) and on devices with different oxide thicknesses and channel dopings help to identify the relative impact of the different physical mechanisms at the origin of HD. A measurement-based and design-oriented methodology is finally developed to compare device types, biases and configurations responding to practical design targets.

Keywords

CMOS analogue integrated circuits; MOSFET; harmonic distortion; semiconductor device measurement; silicon-on-insulator; 0.12 micron; 25 to 220 C; CMOS analog integrated circuits; MOSFET-C analog structures; channel dopings; deep-submicrometer technologies; harmonic distortion; oxide thicknesses; semiconductor device measurements; silicon on insulator technology; CMOS process; CMOS technology; Design methodology; Distortion measurement; Harmonic distortion; High definition video; MOSFET circuits; Performance evaluation; Silicon on insulator technology; Thickness measurement; CMOS analog integrated circuits; MOSFETs; continuous time filters; harmonic distortion; semiconductor device measurements; silicon-on-insulator (SOI) technology;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2005.861725

Filename

1580863