Vertical Power ${\rm H}k$ -MOSFET of Hexagonal Layout

A vertical power MOSFET with hexagonal cells by using high- $k~({\rm H}k)$ insulator (Hk-MOSFET) in voltage-sustaining region is studied. Both cases of the Hk-MOSFET hexagonal cell, one with a semiconductor in the center of each hexagonal cell and another with an insulator in the center, are discussed. The optimized specific on-resistance $(R_{\rm sp})$ of an ${\rm H}k$ -MOSFET for the former case is around 20% smaller than that of using an interdigitated layout. For the latter case, the optimized $R_{\rm sp}$ is further reduced. The theoretical predictions are in good agreement with the numerical results from simulation. An example indicates that the $R_{\rm sp}$ of a hexagonal ${\rm H}k$ -MOSFET for the latter case is nearly two-thirds that of an interdigitated one, and is almost identical to that of an optimized superjunction (SJ) MOSFET with a hexagonal cell under the same breakdown voltage $(V_{B})$ . The $V_{B}$ of an ${\rm H}k$ device is more robust than that of an SJ device to the charge imbalance effect. Although ${\rm H}k$ -MOSFET has a little slower transient response than that of SJ-MOSFET, the body diode reverse recovery behavior is much softer than the latter.