A motion estimator for low bit-rate video codec

Author

Jehng, Yeu-Shen ; Chen, Liang-Gee ; Chiueh, Tzi-Dar

Author_Institution

Dept. of Electr. Eng.. Nat. Taiwan Univ., Taipei, Taiwan

Volume

38

Issue

2

fYear

1992

fDate

5/1/1992 12:00:00 AM

Firstpage

60

Lastpage

69

Abstract

A novel component performing motion estimation is presented. This chip is designed based on the three-step hierarchical search block-matching algorithm and can be applied to image communication on ISDN (integrated services digital network) (H.261 standard), MPEG, TV transmission, HDTV (high-definition television), etc. The practical architectural design techniques and the chip features are discussed. This component has the following features: unified execution steps, low latency delay, low I/O bandwidth, regular hardware structure, and single-chip or cascaded configurations

Keywords

CMOS integrated circuits; codecs; computerised picture processing; digital signal processing chips; video equipment; H.261 standard; HDTV; ISDN; MPEG; TV transmission; cascaded structure; image communication; low I/O bandwidth; low bit-rate video codec; low latency delay; motion estimator; regular hardware structure; single-chip structure; three-step hierarchical search block-matching algorithm; unified execution steps; Algorithm design and analysis; Bandwidth; Communication standards; Delay; HDTV; ISDN; Image communication; Motion estimation; TV; Video codecs;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.142860

Filename

142860