Title :
Race-free clocking of CMOS pipelines using a single global clock
Author :
Renshaw, David ; Lau, Choon How
Author_Institution :
Dept. of Electr. Eng., Edinburgh Univ., UK
fDate :
6/1/1990 12:00:00 AM
Abstract :
A novel, single-phase, race-free CMOS circuit clocking technique, which provides and uses complementary logic, is presented. The clock can be driven by a sinusoidal waveform. This avoids any requirement for transmitting the very-high-frequency components associated with fast clock edges. Such circuits are therefore less sensitive to clock distortion caused by transmission-line effects
Keywords :
CMOS integrated circuits; clocks; pipeline processing; CMOS pipelines; clock distortion; clock edges; complementary logic; global clock; race-free CMOS circuit clocking; sinusoidal waveform; transmission-line effects; Bonding; Clocks; Frequency; Impedance; Jitter; Optical reflection; Optical transmitters; Pipelines; Resistors; Solid state circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
