Title :
A 70-MHz 32-b microprocessor with 1.0-μm BiCMOS macrocell library
Author :
Hotta, Takashi ; Bandoh, Tadaaki ; Hotta, Atsuo ; Nakano, Tetsuo ; Iwamoto, Shoji ; Adachi, Shigemi
Author_Institution :
Hitachi Ltd., Ibaraki, Japan
fDate :
6/1/1990 12:00:00 AM
Abstract :
A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm2 die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz
Keywords :
BIMOS integrated circuits; microprocessor chips; pipeline processing; 1.0 micron; 2.1 W; 32 bits; 70 MHz; 70 MIPS; BiCMOS macrocell library; PLL; RAM; bipolar drivers; clock generator; extensible ROM; five-stage pipeline; microprocessor; sense circuits; BiCMOS integrated circuits; Clocks; Delay; Libraries; Logic circuits; MOS devices; Macrocell networks; Microprocessors; Phase locked loops; Read only memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
