Title :
A reconfigurable parallel signature analyzer for concurrent error correction in DRAM
Author :
Mazumder, Pinaki ; Patel, Janak H. ; Abraham, Jacob A.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fDate :
6/1/1990 12:00:00 AM
Abstract :
An efficient strategy for utilizing a parallel signature analyzer (PSA) for concurrent soft-error correction in DRAMs (dynamic random-access memories) is described. For a two-level w-bit, n-word memory system, the proposed technique needs only one additional chip as opposed to log2w+2 in the conventional Hamming code. Such an error-correction circuit significantly improves the reliability of the memory system
Keywords :
error correction; integrated memory circuits; logic testing; random-access storage; DRAM; concurrent error correction; memory system; n-word memory system; reconfigurable parallel signature analyzer; reliability; soft-error correction; Circuit testing; Compaction; Computer errors; Error analysis; Error correction; Error correction codes; Jacobian matrices; Legged locomotion; Random access memory; Sequential analysis;
Journal_Title :
Solid-State Circuits, IEEE Journal of
