Title :
SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors
Author :
Yamaoka, Masanao ; Tsuchiya, Ryuta ; Kawahara, Takayuki
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo
Abstract :
The deterioration of operating margin and increasing leakage current in SRAM are becoming critical problems with the advance of process scaling. To solve these problems, we propose a low-power SRAM circuit using thin buried-oxide fully depleted silicon-on-insulator transistors. The back-gate bias is introduced to the SRAM circuits and acquires high operating margin and high-speed operation under low supply voltage. The leakage current in stand-by state is reduced. This SRAM achieves 30% faster writing time under low-voltage operation and 90% less stand-by power
Keywords :
SRAM chips; leakage currents; low-power electronics; silicon-on-insulator; SRAM circuit; back-gate bias; expanded operating margin; standby leakage current; thin buried-oxide fully depleted silicon-on-insulator transistors; thin-BOX FD-SOI transistors; Circuits; Energy consumption; Leakage current; Low voltage; Random access memory; Silicon on insulator technology; System-on-a-chip; TV; Transistors; Writing; Back-gate bias; SRAM; low-leakage current; operating margin; thin buried-oxide fully depleted silicon-on-insulator (thin-BOX FD-SOI) transistor;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.882891
