Title :
A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System
Author :
Kim, Hyejung ; Nam, Byeong-Gyu ; Sohn, Ju-Ho ; Woo, Jeong-Ho ; Yoo, Hoi-Jun
Author_Institution :
Korea Adv. Inst. of Sci. & Technol., Daejeon
Abstract :
A 32-bit fixed-point logarithmic arithmetic unit is proposed for the possible application to mobile three-dimensional (3-D) graphics system. The proposed logarithmic arithmetic unit performs division, reciprocal, square-root, reciprocal-square-root and square operations in two clock cycles and powering operation in four clock cycles. It can program its number range for accurate computation flexibility of 3-D graphics pipeline and eight -region piecewise linear approximation model for logarithmic and antilogarithmic conversion to reduce the operation error under 0.2%. Its test chip is implemented by 1-poly 6-metal 0.18-mum CMOS technology with 9-k gates. It operates at the maximum frequency of 231 MHz and consumes 2.18 mW at 1.8-V supply
Keywords :
CMOS digital integrated circuits; computer graphics; fixed point arithmetic; microprocessor chips; 0.18 micron; 1.8 V; 2.18 mW; 231 MHz; 32 bit; 3D graphics pipeline; CMOS technology; antilog-arithmetic conversion; division operations; fixed-point 3D graphics system; logarithmic arithmetic unit; logarithmic number system; mobile 3D graphics system; piecewise linear approximation; reciprocal-square-root operations; square operations; CMOS technology; Clocks; Fixed-point arithmetic; Frequency; Graphics; Piecewise linear approximation; Pipelines; Power system modeling; Semiconductor device modeling; Testing; 3-D graphics; ALU; antilogarithm; logarithmic number system (LNS);
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2006.882887
