The design of analog front ends for 1000BASE-T receivers

This paper explores the design of analog front ends (AFEs) for a 1000BASE-T receiver. We consider having the AFE perform partial equalization or partial echo cancellation in addition to the required low-pass filtering function. Different architectures that can realize one of these two functions are presented, and these architectures are optimized to enable the receiver to achieve the best overall performance. A higher performance AFE enables a lower-complexity digital backend to be used, thereby simplifying the overall receiver. These architectures are compared in terms of power dissipation, chip area, and performance (using system-level simulations). The effects of varying cable lengths are also analyzed. The reductions in ADC resolution, or digital filter length, enabled by these architectures are estimated. Our results show that by properly selecting the AFE architecture, the overall receiver can be simplified without sacrificing performance.