Known good die meets chip size package

The increasing density, functionality, and high speed performance of integrated circuit components are fueling demands for smaller and faster portable electronic systems. Designers are becoming more experienced at cutting size, delays, and costs wherever possible. One area that offers attractive benefits for reducing size and improving performance is in the IC package itself, either eliminating it altogether, or reducing the size to the point where it takes up very little more space than the IC. In that context, chip size packages (CSPs) offer a viable solution to the problem. The electrical performance of a circuit is degraded by any capacitance, inductance, and lead length added to the IC bond pads. In addition to the performance limitations of the IC package itself, the larger footprint of the package implies that the next level of interconnect will also be sub optimal due to size and fanout of the IC interconnections. CSPs address these problems, too