Polynomial complexity algorithms for increasing the testability of digital circuits by testing-module insertion

The authors present a method for increasing the testability of combinational circuits for single stuck-at faults by partitioning the circuit and inserting testing-modules. A testing-module structure that allows lines in the circuit to be logically disconnected is shown. It allows the circuit to be partitioned into independent subcircuits. A test generation algorithm that is based on test set merging is presented. An optimal testing-module placement algorithm is described for fanout free circuits. A special type of circuit with fanout for which optimal testing-module placement can also be performed is defined, and a testing-module placement algorithm for them is outlined. For general fanout circuits, polynomial testing-module placement and test generation algorithms are described. Testing-modules are used for partitioning the circuit into fanout free subcircuits. Test set merging that yields a complete test set for the circuit is described