DocumentCode
807538
Title
16:1 retiming multiplexer for 10 Gbit/s in Si production technology
Author
Znidarsic, F. ; Müllner, E. ; Strunz, R.
Author_Institution
Public Commun. Networks, Siemens AG, Munich, Germany
Volume
32
Issue
3
fYear
1996
fDate
2/1/1996 12:00:00 AM
Firstpage
207
Lastpage
209
Abstract
A 16:1 multiplexer was realised for a 10 Gbit/s data transmission system. Only a single 10 GHz clock is used to generate all internal select and clock signals. No external delay lines are needed to achieve a proper clock signal for output retiming. The data jitter is ~3 ps under worst case operating conditions
Keywords
bipolar digital integrated circuits; clocks; data communication equipment; jitter; multiplexing equipment; timing circuits; 10 Gbit/s; 16:1 retiming multiplexer; Si; Si production technology; clock signal; data jitter; data transmission system; internal select signal;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19960143
Filename
490804
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