• DocumentCode
    807816
  • Title

    Associating CMOS transistors with BDD arcs for technology mapping

  • Author

    Reis, A. ; Robert, M. ; Auvergne, D. ; Reis, R.

  • Author_Institution
    LIRMM, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
  • Volume
    31
  • Issue
    14
  • fYear
    1995
  • fDate
    7/6/1995 12:00:00 AM
  • Firstpage
    1118
  • Lastpage
    1120
  • Abstract
    A novel BDD (binary decision diagram) class that allows a direct association of CMOS transistors with BDD arcs is proposed. This BDD class, terminal suppressed BDDs (TBDDs), allows a direct technology mapping with the aim of automatic leaf cell generation. This is obtained from a straightforward extraction of the cell transistor topology from a TBDD
  • Keywords
    CMOS logic circuits; circuit layout CAD; graph theory; integrated circuit layout; logic CAD; BDD arcs; BDD class; CMOS transistors; automatic leaf cell generation; binary decision diagram; cell transistor topology extraction; direct technology mapping; terminal suppressed BDDs;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19950799
  • Filename
    398567
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=807816