Title :
A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses
Author :
Arima, Yutaka ; Murasaki, Mitsuhiro ; Yamada, Tsuyoshi ; Maeda, Atsushi ; Shinohara, Hirofumi
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
12/1/1992 12:00:00 AM
Abstract :
An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals
Keywords :
CMOS integrated circuits; VLSI; analogue processing circuits; learning (artificial intelligence); neural chips; 0.8 micron; analog storage synaptic weights; double-poly double-metal CMOS technology; neurons; on-chip learning neural network LSI circuit; refreshable analog VLSI neural network chip; synapses; CMOS technology; Capacitors; Circuits; Computer networks; Large scale integration; Large-scale systems; Network-on-a-chip; Neural networks; Neurons; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
