DocumentCode
808087
Title
A refreshable analog VLSI neural network chip with 400 neurons and 40 K synapses
Author
Arima, Yutaka ; Murasaki, Mitsuhiro ; Yamada, Tsuyoshi ; Maeda, Atsushi ; Shinohara, Hirofumi
Author_Institution
Mitsubishi Electr. Corp., Hyogo, Japan
Volume
27
Issue
12
fYear
1992
fDate
12/1/1992 12:00:00 AM
Firstpage
1854
Lastpage
1861
Abstract
An on-chip learning neural network LSI circuit that can refresh the analog storage synaptic weights located on a chip is described. The chip integrates 400 neurons and 40000 synapses with a 0.8-μm double-poly double-metal CMOS technology. This device stores learned information by repeating the refresh process at 200-ms intervals
Keywords
CMOS integrated circuits; VLSI; analogue processing circuits; learning (artificial intelligence); neural chips; 0.8 micron; analog storage synaptic weights; double-poly double-metal CMOS technology; neurons; on-chip learning neural network LSI circuit; refreshable analog VLSI neural network chip; synapses; CMOS technology; Capacitors; Circuits; Computer networks; Large scale integration; Large-scale systems; Network-on-a-chip; Neural networks; Neurons; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.173115
Filename
173115
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